1. Field of the Invention
The present invention relates to the error detection in a data processing system which needs to implement a high-speed transfer of a large volume of data with high reliability, and more specifically to the apparatus and method which judges the legitimacy of the transfer data using a check code in the data processing system in which data and a data block including a check code for the data are divided into a plurality of frames and the divided frames are transmitted.
2. Description of the Related Art
In recent years, the use of fibre channels has become popular as a means for implementing high-speed transfer of a large volume of data between a host computer and a storage apparatus. The storage apparatus comprises a storage device such as a disk device (disk drive) shared by a plurality of host computers and a storage control device which controls data transfer between the host computer and the storage device.
Data in the host computer on the data transmitting side is divided into a plurality of frames of up to 2 k bites. The divided frames are transmitted on the fibre channel link, and are build again to original data by storage apparatus on the data receiving side. At that time, each frame to be transferred is protected from errors by a cyclic redundancy check (CRC), so it is possible to implement data transfer with high reliability.
However, even higher reliability is required for certain uses. To meet such a requirement, the method of protecting the whole data that the host computer prepares with a check code is used in addition to the protection of each frame from errors by CRC.
As the check code, the result obtained by implementing the calculation with an algorithm determined in advance using the data to be protected is used. CRC code is an example of the check codes, and is sometimes used for this particular purpose, but other check codes (other cyclic codes, etc.) are sometimes used for said purpose.
In this protection method, the host computer transmits user data 101 with a check code 102 added as a data block 103, as shown in FIG. 1A. On the fibre channel link, the data block 103 is divided into a plurality of frames 104 (104a, 104b, 104c, 104d), and each frame is protected by CRC and is transferred to the storage control device. Since the check code 102 is usually smaller than the data of a frame, it is contained in the last frame and is transferred.
The storage apparatus performs the CRC of each frame received, and builds each frame back to an original data block 103, and after then implements the calculation of the same algorithm as that the host computer uses to produce the check code 102, for the user data 101. The calculation result obtained thereby should be the same as the check code 102 that the host computer has added, so that the legitimacy of the user data 101 can be judged by comparing the calculation result with the check code 102.
FIG. 1B shows the block diagram of the data processing system which employs such a protection method. The data processing system shown in FIG. 1B comprises one or more host computers 111, a communication network 112, a storage control device 113, and one or more disk devices 114.
The host computer 111 is connected to the storage control device 113 via the communication network 112, and the disk device 114 is connected to the storage control device 113. The storage control device 113 and the disk device 114 constitute the storage apparatus.
The communication network 112 is equipped with switches, for example, in accordance with the link of the fibre channel. In general, a plurality of host computers 111 are connected to the communication network 112.
The storage control device 113 comprises a processor 121, a controller 122, and a data buffer 123, and the controller 122 comprises a check code judgment circuit 131 and a CRC check circuit 132.
The storage control device 113 has interfaces for the host computer 111 and the disk device 114, and receives data from the host computer 111 via the communication network 112.
The frames of the fibre channel comprise a header part, a data part, and a CRC code, as shown in FIG. 1A. The controller 122, when receiving the frames, checks whether there is any error in the frames by the CRC check circuit 132. At the same time, the controller 122 stores the data part of the frame in the data buffer 123, and transfers the header part to the processor 121. Information necessary to specify a part of which data block a frame received is and to build the frame back to original data is included in the header part.
The storage control device 113 repeats this operation and receives one frame after another from the host computer 111. When the whole data block of one piece of user data is stored in the data buffer 123, the processor 121 starts the check code judgment circuit 131.
The check code judgment circuit 131 reads the data block by a specific quantity (for example, 4 bites) from the data buffer 124, and repeats the operation which applies the algorithm determined in the read data, and produces the check code of the data block. Then, the check code judgment circuit 131 judges the validity of the check code obtained and notifies the processor 121 of the judgment result.
<Jpn. unexamined patent application publication No. 2001-144629> discloses apparatus which corrects errors of an optical disk, etc. <<Jpn. unexamined patent application publication No. 5-091072>> discloses method of transferring data between one terminal and another terminal using CRC, <<<Jpn. unexamined patent application publication No. 5-035624>>> discloses radio data transfer using an error correction code, <<<<U.S. Pat. No. 5,630,054>>>> relates to the error judgment of a storage device using CRC.
<Jpn. unexamined patent application publication No. 2001-144629>
<<Jpn. unexamined patent application publication No. 5-091072>>
<<<Jpn. unexamined patent application publication No. 5-035624>>>
<<<<U.S. Pat. No. 5,630,054>>>>
There are the following problems in the conventional check code judgment method described above.
According to the sequence of the conventional check code judgment, after all the frames of the data block in user data are received, the check code judgment circuit is started, and the check codes are judged, so it takes a considerable time until the judgment of the check codes are completed. In order to finish the judgment promptly, it can be considered to start the check code judgment circuit every time a frame is received and calculate the interim result of the data received.
However, on the fibre channel link, it is not that the frames of one piece of user data are transferred continuously, as shown in FIG. 1C but user data from a plurality of host computers is divided into frames and the divided frames are transferred in an interleaving state.
In the example shown in FIG. 1C, data blocks 141a, 141b and 141c from the host computers 111a, 111b and 111c (user data A, B and C) are divided into three frames and the divided frames are transferred to the storage control unit 113. From the data stored in these frames, original user data A, B and C are built and stored in the disk device 114.
In this case, there is an advantage in that if the check code judgment circuit is started every time each frame is received, the judgment of the check code for one piece of user data (for example, user data A) finishes promptly. During that period, however, outstanding user data (for example, user data B and C) cannot be inputted into the check code judgment circuit. Consequently, the judgment of outstanding user data is made to wait until the judgment of preceding user data comes to an end, so this method cannot be a good enough solution to solve the problem.